דרושים»חשמל ואלקטרוניקה» Senior Verification Engineer

לפני 15 שעות חברה חסויה Location: Job Type: Develop advanced verification environments using SystemVerilog and UVM Write, run, and debug testbenches to ensure complete functional coverage Drive pre-silicon and in-lab debug activities to resolve complex issues Collaborate with RTL, architecture, and physical design teams to achieve design closure Support methodology development, scripting, and automation to enhance productivity Contribute to the success, powering the next generation of Internet infrastructureRequirements: 6+ years of experience in digital logic design verification Advanced knowledge of SystemVerilog and UVM Strong debug skills both pre-silicon and in-labThis position is open to all candidates. Hide