דרושים»חשמל ואלקטרוניקה» Staff Physical STA Expert

לפני 18 שעות חברה חסויה Location: Job Type: As a Staff Physical STA Expert, you will hold the keys to silicon success. You will be leading the STA activities end-to-end from Chip partition, Time budgeting through signoff of all the chips we develop. You will build and lead the STA team to run several chips signoffs in parallel. In addition, You will define the sign-off methodology for chips that power the worlds most advanced AI clusters. You will act as the central nervous system of the design process, bridging the gap between Architecture, Design, DFT, and Physical Design to ensure our high-performance silicon meets the aggressive timing targets required for next-generation connectivity.

Key Responsibilities

Take full ownership of the STA flow and sign-off methodologies. You will establish the rigorous criteria that ensure our products succeed in the most demanding data center environments Collaborate closely with Architecture, Design, DFT, and Backend teams. You will lead timing reviews and work closely with block owners to navigate the path to sign-off convergence Develop, optimize, and manage complex SDC constraints from the ground up, ensuring they are robust across multi-scenario environments Tackle the challenges of cross-chip clock distribution networks and sophisticated margining techniques, ensuring robust silicon across all process corners Have a passion for better workflows? Youll participate in design methodology improvements and tool automation, utilizing both industry-standard EDA tools and in-house automation to make our sign-off process faster and smarterRequirements: B.Sc. in Electrical Engineering or Computer Engineering 8+ years of deep, hands-on experience in Static Timing Analysis (STA) at leading semiconductor companies, specifically working on advanced process technologies Deep expertise in multi-scenario STA, timing/SDC constraint development and verification. You have a "full-chip" perspective, managing both complex macro-level designs and top-level integration Solid understanding of advanced margining methodologies, including OCV, AOCV, and POCV, from synthesis through to final sign-off Solid knowledge of physical design flows (P&R, Physical Verification) and how they intersect with timing closureThis position is open to all candidates. Hide