FPGA consultant ID:405

• för 48 minuter sedan
• 1 min läsning

Requirements:

·                 4+ years of experience in HDL dea multi-clock environment for FPGA implementation

·                 Worked with medium to large designs

·                 Experience of deg and working with fully custom, in-house built System Verilog modules

·                 Experience of working with integration and configuration of FPGA Vendor IPs

·                 Optimization of calculation heavy algorithms on RTL level

o              Experienced in timing-critical FPGA design and timing closure

o              Experience in writing timing constraints for multi-clock domain designs

·                 Verification using System Verilog and Python

·                 Worked with SOC FPGAs, i.e. with hardened CPU

·                 High speed IO, DDR, PCIe and MIPI

·                 Board bring-up & debugging

o              Use of Vivado ILA

·                 Scripting, mainly in Python

·                 Electronics and Electronic lab tools fundamentals (Multimeter, Osciloscope)

·                 Digital Signal Processing fundamentals

·                 Comfortable with simulation tools and writing testbenches

·                 Good at documenting full designs

Good to have:

·                 Experience of High Level Synthesis

·                 Experience of MATLAB and Simulink

·                 AMD Zynq UltraScale+

Personality:

100% onsite