Wafer-Level Automotive IC Packaging

Budget: ₹12500 - ₹37500

I need a complete wafer-level packaging approach tailored for an automotive electronics device where high reliability is the overriding priority. The goal is to move from concept to a production-ready package that can withstand the thermal and mechanical stresses found under-the-hood and meet typical automotive qualification standards such as AEC-Q100.

Scope of work • Evaluate the die’s electrical, thermal, and mechanical needs and translate them into a wafer-level package stack-up, material set, and process flow. • Model key stress points and propose design tweaks or material changes that maximise reliability; maintaining a compact outline or improved heat dissipation would be welcome bonuses if they do not compromise the main reliability target. • Deliver a clear manufacturing roadmap that covers mask XXXX XXXX, key process parameters, and inline control points. • Define the reliability test plan, expected pass criteria, and any corner-case risks so that my internal team can align our qualification schedule. • Provide all drawings, Gerbers/ODB++, and simulation files so we are able to hand them straight to an OSAT for quotation.

Acceptance criteria • Package concept must be wafer-level, not wire-bond or flip-chip hybrids. • Design must show calculated or simulated margins that meet or exceed AEC-Q100 Grade 0 thermal cycling and high-temperature operating life expectations. • Documentation is complete enough for an external fabricator to begin tooling with no open questions.

If you have a proven track record in automotive-grade WLP designs, I would like to review a brief outline of your past projects and the design tools you normally deploy before we proceed.