Junior Verification Engineer

About the Role: We are seeking a motivated Junior Verification Engineer to join our VLSI design and verification team. This is an excellent opportunity for new graduates with strong academic training in digital design, verification methodologies, and SystemVerilog/UVM.

Responsibilities: Develop and execute verification testbenches using Verilog/SystemVerilog and UVM Implement functional and constrained-random tests for block-level and SoC-level designs Create coverage models (functional, code, assertion-based) and drive coverage closure Debug simulation failures, interface mismatches, and RTL issues Write and maintain scoreboards, monitors, agents, drivers, and checkers in UVM Review design specifications, extract test requirements, and build verification plans Run regressions, triage failures, and document results Collaborate closely with RTL designers, DFT, backend, and system architects

Required Qualifications: B.Sc. or M.Sc. in Electrical/Computer Engineering or related field Strong academic background in digital logic, computer architecture, and VLSI design Hands-on experience with Verilog and SystemVerilog (labs, projects, internship) Basic understanding of UVM methodology Familiarity with simulation tools (VCS, QuestaSim, Xcelium or similar) Ability to read and understand RTL code Good analytical and debugging skills Strong motivation to grow in advanced functional verification

Nice-to-Have Skills: Coursework or project experience with UVM testbench development Familiarity with assertion-based verification (SVA) Basic scripting (Python, Perl, Shell, TCL) Experience with coverage-driven verification Exposure to SoC-level interfaces (AXI, PCIe, DDR, Ethernet, SPI, I2C)

What We Offer: Full training in modern verification methodologies (UVM, SVA, CRV) Work with cutting-edge IPs and SoC architectures Mentorship from senior verification and architecture teams Clear growth path toward UVM specialist, verification lead, or architect