דרושים»הנדסה» ASIC Design Engineering Technical Leader

לפני 12 שעות חברה חסויה Location: Job Type: Write and review micro-architecture specifications

Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements

Contribute to full chip integration, timing methodology, and analysis

Collaborate with verification engineers to resolve bugs and achieve coverage closure

Work with the physical design team to close timing and PnR issues

Support design methodology evolution and best practices

Perform debug, root-cause analysis, and post-silicon validation in the labRequirements: B.Sc./M.Sc. in Electrical Engineering from a top university

​Minimum of 8 years of proven experience in a relevant field

RTL design experience

Familiarity with UVM and functional verification methodologiesThis position is open to all candidates. Hide