דרושים»תוכנה» Senior/ Staff Physical Design Engineer - CAD Extraction

לפני 18 שעות חברה חסויה Location: Job Type: we're seeking a highly skilled Physical Design CAD Engineer specializing in CAD Extraction to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, implementing the parasitic extraction (PEX) methodologies and flows for chips that power the world's largest AI clusters. As a foundational member of the team, you will be responsible for the accuracy and efficiency of our extraction environment, ensuring that our high-speed designs are modeled with the highest precision from RTL to GDSII.

Key Responsibilities

Develop, qualify, and maintain automated RC extraction flows for high-performance AI SoCs Own the setup and validation of foundry technology files (e.g., StarRC/Quantus techfiles, TLU+, ITF) across various process corners Perform correlation studies between different extraction tools and 3D field solvers (e.g., Raphael, QuickCap) to ensure modeling accuracy Collaborate closely with the Signal Integrity (SI) and Power Integrity (PI) teams to provide accurate parasitic data for critical high-speed nets and power grids Implement automated scripts (Tcl/Python) to streamline extraction regressions, data parsing, and PEX-to-STA (Static Timing Analysis) handoffs Analyze the impact of layout effects (LDE) and parasitics on timing and power, providing feedback to the implementation team to optimize PPA Interface with EDA vendors and foundries to resolve extraction tool bugs and methodology gaps related to advanced nodes (5nm/3nm)Requirements: Bachelors degree in Electrical Engineering or a related technical field 5+ years of hands-on experience in Physical Design CAD or Physical Verification with a heavy focus on parasitic extraction Expert proficiency with industry-standard extraction tools such as Synopsys StarRC, Cadence Quantus (QRC), or Siemens Calibre xACT Strong scripting skills in Tcl and Python for flow automation and database manipulation Deep understanding of semiconductor physics, interconnect modeling, and the impact of parasitics on timing, EM (Electromigration), and IR drop Proven experience in validating tech files and running extraction for complex, multi-million gate designsThis position is open to all candidates. Hide